This invention relates to an electronic assembly, such as a multi-chip module. In particular, the present invention relates to testing an electronic assembly having an Application Specific Integration Circuit (ASIC).
Testing an electronic assembly is a necessary step to ensure the accuracy and reliability of the assembly. Currently, testing involves long complicated algorithms and expensive test systems that cannot be executed at system speed. Current test methods are intrusive and interfere with the operation of the electronic assembly.
A static interconnect test is used to obtain test data. However, the test must be executed in a slow clock input environment, which does not detect speed-related defects. In addition, the test results must be monitored serially at an output by external equipment.
A test exists that can be performed at speed in the system""s clock environment, but not at true system speed. In xe2x80x9ctruly at-speedxe2x80x9d testing, testing is performed in the system""s true native clock environment and at system clock frequencies. One drawback to such a system is that the test is intrusive to the functional operation of the electronic assembly. Bypass structures in the electronic assembly""s ASIC burn power and burden critical systems with timing penalties during the test.
It is an object of the present invention to detect speed-related defects in an electronic assembly at system and sub-system levels.
It is another object of the present invention to provide true at-speed testing of an electronic assembly.
The present invention is a system and method for detecting speed related defects in an electronic assembly at system and sub-system levels. The system of the present invention applies to ASICs designed with registered I/O""s to provide true at-speed testing of the electronic assembly. The system also includes an interconnect test engine and a test access port controller.
The method of the present invention generates binary progressive scan patterns for the output registers of one ASIC that are scanned and captured at the input registers of another ASIC. The test results are stored in a multiple input shift register (MISR) where they can be accessed for examination and diagnostic evaluations.
The system and method of the present invention allows all of the ASICs of the electronic assembly to participate simultaneously. The method of the present invention includes a two vector three scan or capture operation that does not require complex logic or algorithms. Because the method and system of the present invention are non-intrusive, there are no timing penalties to the functional signals of the electronic assembly and there is no extra power consumption by the test during the functional operations of the electronic assembly.
One advantage of the present invention is that because the self-test is autonomous within each ASIC, no further external components are added to the circuitry to implement a test. The system can satisfy xe2x80x9cat speedxe2x80x9d interconnect tests in an electronic assembly with ASICs having unidirectional input and output pins. The direction of these pins can be hardwired in an ASICs. Or, in case when transceivers are available, the direction can be programmed by using the TAP controller. Multiple passes of the test sequence from this invention will allow both directions to be tested.
A more complete understanding of the present invention can be determined from the following detailed description when taken in view of the attached drawings and the claims appended hereto.